Finally,the interface between microprocessor and RSA,or between RSA and EEPROM is implemented to realize the whole system function. The design of IIC part is depicted with Verilog HDL. By Verilog-XL tools,behavior simulation is achieved.

• 对于RSA模块和外界及安全芯片存储器EEPROM的通讯接口IIC模块的软核设计，划分了具体的模块，针对每个模块使用Verilog HDL 语言进行描述，通过Verilog-XL完成了软件平台上的行为级仿真，实现了系统的整体协同工作。