A Low Power Design of DSP Processor Bus 一种降低DSP芯片总线功耗的设计方案
A Low power Design of PDP Drving Waveform 一种低功耗的PDP驱动波形设计
Adaptive Clock Gating Technique for Low Power IP Core Design in SoC 应用于片上系统中低功耗IP核设计的自适应门控时钟技术
In this paper a low power 2D DCT/IDCT processor is presented. 设计了一种低功耗的2D DCT/IDCT处理器。
Described was a design of a serial real-time clock chip with I2C bus interfaces,which was a low power,full binary-coded decimal(BCD) clock/calendar chip,and whose address and data were transferred serially through an I2C bidirectional bus. 论述了一种采用I2C总线接口的串行实时时钟芯片的设计方法.