To acquire the clock phase and to assure the duty cycle of the clock, it results in the growth of the phase-locked loops (PLLs), delay-locked loops (DLLs), and pulsewidth control loops (PWCLs).

• 为了能够锁定一时脉讯号的相位以及工作周期，锁相迴路、延迟锁定迴路、以及脉波宽度控制迴路均被深入的研究。