This paper states design of layout and examination of DRC (Design Rule Checking) and LVS (Layout Versus Schematic) and extract of RC parasitic parameter of a kind of memory of 16 digit.

• 阐述了对一种16位存储器版图设计中的DRC(DesignRuleChecking)即"设计规则检查"和LVS(LayoutVersusSchematic)即"版图和电路比较"、以及RC寄生参数的提取.