This paper discusses the theory of AES algorithm,and describes its process and structure with Verilog HDL. Based on the structure,it completes the FPGA design of AES encryption and decryption algorithm when block length is 128bits.

• 分析了高级加密标准算法(AES)的原理,并在此基础上对AES的硬件实现方法进行研究,用硬件设计语言(Verilog HDL)描述了该算法的基本过程和结构,完成了分组长度为128比特的AES加/解密芯片设计。