This architecture combines the advantage of Multi-Bus and TMR structure which despite possible failure of voter that may cause no output of system.

• 此架构有效的整合了多管线备份架构及三组态容错架构两者的优点，排除了当三组态备份架构中多数表决控制器出现异常状态时导致全系统无输出讯号之可能性。