This ADC adopts 9 stage , 1.5bit/stage pipeline architecture, with 10 bit resolution and speed no less than 20MS/s, implemented in CSMC 0.60um DPDM CMOS process.

• 本文设计的是10位20MHz流水线结构的模数转换器；设计基于CSMC 0.；6um CMOS混合信号工艺。