On the basis ofthe analysis of features of Verilog HDL and RTL description, this paper shows themethod of the construction of the module library and the conversion from RTL HDLdescription to gate-level description.

• 文中分析了Verilog HDL语言和RTL描述的特点，介绍了该编译器解析Verilog HDL描述、创建功能模块类库以及将Verilog HDL的RTL描述转化为无层次分块的门级描述的基本原理和主要问题的解决策略。