Efficiently using of dynamic compound gates,clock delayed domino logic and FET scaling technique,the modified adder architecture achieved good performance.

• 基于改进的加法器结构 ；有效地使用动态复合门、时钟延迟多米诺逻辑和场效应管尺寸缩小技术 ；可以取得良好的电路性能 .